JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met.
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High Temperature storage test is typically used to determine the effect of time and temperature, under storage conditions, for thermally activated failure mechanisms of solid state electronic devices, including nonvolatile memory devices data retention failure mechanisms.
During the test elevated temperatures accelerated test conditions are used without electrical stress applied. This test may be destructive, depending on Time, Temperature and Packaging if any.
As a minimum the following items should be taken into consideration: 1 Melting point of metals present, especially solder. Degradation of metals includes metallurgical interfaces. For example Glass Transition Temperature and thermal stability in air of any polymeric materials. For example: Charge loss in Nonvolatile memories. Other conditions and durations may be used as appropriate. The devices may be returned to room ambient conditions for interim electrical measurements. Intermediate measurements are optional unless otherwise specified.
The electrical test measurements shall consist of parametric and functional tests specified in the applicable procurement document. For nonvolatile memories, the data specified data retention pattern must be written initially, and then subsequently verified without re-writing. For nonvolatile memories, the specified data retention pattern shall be verified before and after storage.
A margin test may be used to detect data retention degradation. Cosmetic package defects and degradation of lead finish, or solderability are not considered valid failure criteria for this stress. If the change to a concept involves any words added or deleted excluding deletion of accidentally repeated words , it is included. Some punctuation changes are not included.
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JEDEC JESD 22-A103